//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-19122697
// Cuda compilation tools, release 7.0, V7.0.17
// Based on LLVM 3.4svn
//

.version 4.2
.target sm_32
.address_size 64

	// .globl	KernelBandwidth

.visible .entry KernelBandwidth(
	.param .u64 KernelBandwidth_param_0,
	.param .u64 KernelBandwidth_param_1
)
{
	.reg .pred 	%p<2>;
	.reg .f32 	%f<2>;
	.reg .s32 	%r<13>;
	.reg .s64 	%rd<26>;


	ld.param.u64 	%rd2, [KernelBandwidth_param_0];
	ld.param.u64 	%rd3, [KernelBandwidth_param_1];
	cvta.to.global.u64 	%rd1, %rd2;
	mov.u32 	%r1, %tid.x;
	cvt.u64.u32	%rd4, %r1;
	mov.u32 	%r2, %ntid.x;
	mov.u32 	%r3, %tid.y;
	mul.wide.u32 	%rd5, %r3, %r2;
	mov.u32 	%r4, %ntid.y;
	mul.wide.u32 	%rd6, %r4, %r2;
	mov.u32 	%r5, %tid.z;
	cvt.u64.u32	%rd7, %r5;
	mul.lo.s64 	%rd8, %rd7, %rd6;
	mov.u32 	%r6, %ntid.z;
	cvt.u64.u32	%rd9, %r6;
	mul.lo.s64 	%rd10, %rd9, %rd6;
	mov.u32 	%r7, %ctaid.x;
	cvt.u64.u32	%rd11, %r7;
	mul.lo.s64 	%rd12, %rd11, %rd10;
	mov.u32 	%r8, %nctaid.x;
	cvt.u64.u32	%rd13, %r8;
	mul.lo.s64 	%rd14, %rd13, %rd10;
	mov.u32 	%r9, %ctaid.y;
	cvt.u64.u32	%rd15, %r9;
	mov.u32 	%r10, %nctaid.y;
	mov.u32 	%r11, %ctaid.z;
	mul.wide.u32 	%rd16, %r11, %r10;
	add.s64 	%rd17, %rd16, %rd15;
	mul.lo.s64 	%rd18, %rd14, %rd17;
	add.s64 	%rd19, %rd5, %rd4;
	add.s64 	%rd20, %rd19, %rd8;
	add.s64 	%rd21, %rd20, %rd12;
	add.s64 	%rd22, %rd21, %rd18;
	rem.s64 	%rd23, %rd22, %rd3;
	shl.b64 	%rd24, %rd23, 4;
	add.s64 	%rd25, %rd1, %rd24;
	ld.global.f32 	%f1, [%rd25];
	setp.neu.f32	%p1, %f1, 0f4640E400;
	@%p1 bra 	BB0_2;

	mov.u32 	%r12, 0;
	st.global.u32 	[%rd1], %r12;

BB0_2:
	ret;
}