//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-19122697
// Cuda compilation tools, release 7.0, V7.0.17
// Based on LLVM 3.4svn
//

.version 4.2
.target sm_30
.address_size 32

	// .globl	KernelBandwidth

.visible .entry KernelBandwidth(
	.param .u32 KernelBandwidth_param_0,
	.param .u32 KernelBandwidth_param_1
)
{
	.reg .pred 	%p<2>;
	.reg .f32 	%f<2>;
	.reg .s32 	%r<24>;


	ld.param.u32 	%r2, [KernelBandwidth_param_0];
	ld.param.u32 	%r3, [KernelBandwidth_param_1];
	cvta.to.global.u32 	%r1, %r2;
	mov.u32 	%r4, %ctaid.z;
	mov.u32 	%r5, %nctaid.y;
	mov.u32 	%r6, %ctaid.y;
	mad.lo.s32 	%r7, %r4, %r5, %r6;
	mov.u32 	%r8, %nctaid.x;
	mov.u32 	%r9, %ctaid.x;
	mad.lo.s32 	%r10, %r7, %r8, %r9;
	mov.u32 	%r11, %ntid.z;
	mov.u32 	%r12, %tid.z;
	mad.lo.s32 	%r13, %r10, %r11, %r12;
	mov.u32 	%r14, %ntid.y;
	mov.u32 	%r15, %tid.y;
	mad.lo.s32 	%r16, %r13, %r14, %r15;
	mov.u32 	%r17, %ntid.x;
	mov.u32 	%r18, %tid.x;
	mad.lo.s32 	%r19, %r16, %r17, %r18;
	rem.s32 	%r20, %r19, %r3;
	shl.b32 	%r21, %r20, 4;
	add.s32 	%r22, %r1, %r21;
	ld.global.f32 	%f1, [%r22];
	setp.neu.f32	%p1, %f1, 0f4640E400;
	@%p1 bra 	BB0_2;

	mov.u32 	%r23, 0;
	st.global.u32 	[%r1], %r23;

BB0_2:
	ret;
}